In the fabrication of PNP transistors in silicon integrated circuits, it is known to implant aluminum into an N-type silicon substrate and to diffuse the aluminum into the substrate to create a P well in the silicon. Aluminum is chosen because it rapidly diffuses into silicon and is a P type dopant that can convert the N type substrate to P type.
The doping in the P well is adjusted to determine the collector characteristics for the PNP transistor that will be created therein. The PNP transistor is completed by diffusing an N type base layer into the P well and a P+ emitter region is then diffused within the N type base. Thus, a double diffused transistor is produced having the conventional vertical construction of a planar structure.
Conventional vertical planar NPN transistors are created in the N type silicon substrate to provide complementary transistors. When the NPN and PNP transistors are produced in a silicon epitaxial layer they can be isolated using the conventional well-known PN junction isolation process and they can be interconnected into a conventional monolithic integrated circuit.
The creation of such transistors is described in my copending patent application Ser. No. 853,530, now U.S. Pat. No. 4,940,671 which was filed Apr. 18, 1986, and is assigned to the assignee of the present invention. This patent application is titled A High Voltage Complementary NPN/PNP Process and was coinvented with J. Barry Small. In a further development, which was coinvented with Dean C. Jennings U.S. Pat. No. 4,910,160 issued on Mar. 20, 1990 to the assignee of the present invention. This patent is titled Complementary PNP/NPN Power Transistor Process. The above application and patent both teach the ion implantation of aluminum into N type epitaxial silicon where the aluminum is diffused a substantial distance into the silicon. The teachings in the application and patent are incorporated herein by reference.
While not taught in the above references, the IC devices being produced often require capacitors as circuit elements. Capacitors can be created using reverse biased PN junctions. For example, a junction can be created by diffusing a heavily doped N++ layer into the silicon P well to create an abrupt PN junction. When reverse biased such a junction can display substantial capacitance per unit area. An even higher capacitance can be realized by preceding the N+ layer with a layer of P+ material having lower resistivity than the P well itself. However, it has been discovered that such capacitors may have high leakage currents when fabricated into aluminum implanted silicon. Furthermore, this leakage tends to grow worse with time.